1. Technical Field
The present disclosure relates to fabrication of metal oxide semiconductor field effect transistors (MOSFETs) in integrated circuits.
2. Description of the Related Art
An example of a scanning electron microscope (SEM) image of a MOSFET transistor built on a silicon substrate is shown in FIG. 1. The MOSFET transistor is a three-terminal electronic switching device in which an electric potential applied to a gate terminal controls the flow of current in a channel region between a source terminal and a drain terminal. The structure of the gate in a silicon MOSFET is that of a parallel plate capacitor in which the dielectric layer between the plates is a very thin, fragile, layer of silicon dioxide, sometimes as thin as about 10-20 Å. The purity and integrity of the gate oxide is a critical factor that determines device performance. The gate “plate” is typically made of polycrystalline silicon (polysilicon).
The source and drain are regions of the substrate that are electrically altered (doped) to have an excess of positive charge (PMOS) or negative charge (NMOS). Doping processes tend to be high energy processes that entail either diffusion of dopant atoms at extreme temperatures, or ion implantation of dopant atoms that are accelerated to high velocities. A common dopant used for NMOS devices, for example, is phosphorous, which can be introduced to the substrate in the form of a thin film of phosphorous pentoxide (P2O5) deposited on the silicon surface. Phosphorous atoms from the P2O5 film can be driven deeper into the silicon substrate by heating, to accelerate the diffusion process. The gate structure is typically fabricated prior to doping the source and drain regions, in part so that the gate structure can serve as a mask for the source and drain doping process.
One drawback of this fabrication sequence is that the gate oxide is vulnerable to damage from subsequent process steps, including high energy doping processes, film removal steps, and surface cleaning steps. During these removal and cleaning steps, gate oxide can be eroded laterally by various etchants, including hydrofluoric (HF) acid. The transistor shown in FIG. 1 exhibits this lateral erosion of the gate oxide, which can reduce transistor performance. If the gate oxide dielectric is undercut too far, relative to the edge of the overlying polysilicon gate, the dielectric can become ineffective and charge can leak from the poly gate to the substrate, causing degradation in transistor performance, and threatening product yields. Therefore, process flow solutions that mitigate gate-to-substrate leakage are of considerable interest.